ST92F120JR9T datasheet(257/320 Pages) STMICROELECTRONICS

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J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.8.5 Interrupt Features

The JBLPD has six interrupt sources that it han-

dles using the internal interrupts protocol. Other

two interrupt sources (REOB and TEOB) are relat-

ed to the DMA feature (See Section 10.8.6 DMA

Features).

No external interrupt channel is used by the

JBLPD.

The dedicated registers of the JBLPD should be

loaded with appropriate values to set the interrupt

vector (see the description of the IVR register), the

interrupt mask bits (see the description of the IMR

scription of the STATUS and PRLR registers).

The interrupt sources are as follows:

– The ERROR interrupt is generated when the ER-

ROR bit of the STATUS register is set. This bit is

set when the following events occur: Transmitter

Timeout, Transmitter Data Underflow, Receiver

Data Overflow, Transmit Request Aborted, Re-

ceived Break Symbol, Cyclic Redundancy Check

Error, Invalid Frame Detect, Invalid Bit Detect (a

more detailed description of these events is giv-

en in the description of the ERROR register).

– The TLA interrupt is generated when the trans-

mitter loses the arbitration (a more detailed de-

scription of this condition is given in the TLA bit

description of the STATUS register).

– The EODM interrupt is generated when the

JBLPD detects a passive level on the VPWI line

longer than the minimum time accepted by the

standard for the End Of Data symbol (a more de-

tailed description of this condition is given in the

EODM bit description of the STATUS register).

– The EOFM interrupt is generated when the

JBLPD detects a passive level on the VPWI line

longer than the minimum time accepted by the

standard for the End Of Frame symbol (a more

detailed description of this condition is given in

the EOFM bit description of the STATUS regis-

ter).

– The RDRF interrupt is generated when a com-

plete data byte has been received and placed in

the RXDATA register (see also the RDRF bit de-

scription of the STATUS register).

– The REOB (Receive End Of Block) interrupt is

generated when receiving using DMA and the

last byte of a sequence of data is read from the

JBLPD.

– The TRDY interrupt is generated by two condi-

tions: when the TXOP register is ready to accept

a new opcode for transmission; when the trans-

mit state machine accepts the opcode for trans-

mission (a more detailed description of this

condition is given in the TRDY bit description of

the STATUS register).

– The TEOB (Transmit End Of Block) interrupt is

generated when transmitting using DMA and the

last byte of a sequence of data is written to the

JBLPD.

10.8.5.1 Interrupt Management

To use the interrupt features the user has to follow

these steps:

– Set the correct priority level of the JBLPD

– Set the correct interrupt vector

– Reset the Pending bits

– Enable the required interrupt source

Note: It is strongly recommended to reset the

pending bits before un-masking the related inter-

rupt sources to avoid spurious interrupt requests.

The priority with respect the other ST9 peripherals

is programmable by the user setting the three

most significant bits of the Interrupt Priority Level

tained by setting all the bits (this priority level is

never acknowledged by the CPU and is equivalent

to disabling the interrupts of the JBLPD); the high-

est interrupt priority is programmed resetting the

bits. See the Interrupt and DMA chapters of the

datasheet for more details.

When the JBLPD interrupt priority is set, the prior-

ity between the internal interrupt sources is fixed

by hardware as shown in Table 48.

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