ST92F120JR9T datasheet(186/320 Pages) STMICROELECTRONICS

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SERIAL COMMUNICATIONS INTERFACE (SCI)

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.3 SCI Operating Modes

10.5.3.1 Asynchronous Mode

In this mode, data and clock can be asynchronous

(the transmitter and receiver can use their own

clocks to sample received data), each data bit is

sampled 16 times per clock period.

The baud rate clock should be set to the

÷16 Mode

and the frequency of the input clock (from an ex-

ternal source or from the internal baud-rate gener-

ator output) is set to suit.

10.5.3.2

Asynchronous

Mode

with

Synchronous Clock

In this mode, data and clock are synchronous,

each data bit is sampled once per clock period.

For transmit operation, a general purpose I/O port

pin can be programmed to output the CLKOUT

signal from the baud rate generator. If the SCI is

provided with an external transmission clock

source, there will be a skew equivalent to two

INTCLK periods between clock and data.

Data will be transmitted on the falling edge of the

transmit clock. Received data will be latched into

the SCI on the rising edge of the receive clock.

Figure 90. Sampling Times in Asynchronous Format

2345

789

SDIN

rcvck

rxd

rxclk

VR001409

LEGEND:

SIN:

rcvck:

rxd:

rxclk:

Serial Data Input line

Internal X16 Receiver Clock

Internal Serial Data Input Line

Internal Receiver Shift Register Sampling Clock

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