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ST7LITE05 bảng dữ liệu(PDF) 102 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
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13.11 8-BIT ADC CHARACTERISTICS
TA = -40°C to 125°C, unless otherwise specified
Figure 86. RAIN max. vs fADC with CAIN=0pF
3)
Figure 87. Recommended CAIN/RAIN values
4)
Figure 88. Typical Application with ADC
Notes:
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k
Ω). Data
based on characterization results, not tested in production.
2. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.
3.CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
4. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization and to allow
the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fADC
ADC clock frequency
4
MHz
VAIN
Conversion voltage range
VSS
VDD
V
RAIN
External input resistor
10 1)
k
Ω
CADC
Internal sample and hold capacitor
VDD=5V
3
pF
tSTAB
Stabilization time after ADC enable
fCPU=8MHz, fADC=4MHz
0 2)
µs
tCONV
Conversion time (tSAMPLE+tHOLD)3
tSAMPLE Sample capacitor loading time
4
1/fADC
tHOLD
Hold conversion time
8
0
5
10
15
20
25
30
35
40
45
010
30
70
CPARASITIC (pF)
4 MHz
2 MHz
1 MHz
0.1
1
10
100
1000
0.01
0.1
1
10
fAIN(KHz)
Cain 10 nF
Cain 22 nF
Cain 47 nF
AINx
ST72XXX
VDD
IL
±1
µA
VT
0.6V
VT
0.6V
CADC
3pF
VAIN
RAIN
8-Bit A/D
Conversion
2k
Ω(max)
CAIN
1



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