ST7263B datasheet(114/132 Pages) STMICROELECTRONICS

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ST7263B

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13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPÜ, and TA unless otherwise specified.

Figure 72. Typical Application with RESET pin 7)

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V, not tested in production.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/

O ports and control pins) must not exceed IVSS.

5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-

scribed in Figure 73). This data is based on characterization results, not tested in production.

6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

7. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

VIH

Input High Level Voltage

0.7xVDD

VDD

VIL

Input Low Voltage

VSS

0.3xVDD

Vhys

Schmitt trigger voltage hysteresis 3)

400

VOL

Output low level voltage 4)

(see Figure 74, Figure 75)

VDD=5V

IIO=5mA

0.8

IIO=7.5mA

1.3

RON

Weak pull-up equivalent resistor 5)

VIN=VSS

VDD=5V

100

Ω

tw(RSTL)out Generated reset pulse duration

External pin or

internal reset sources

1/fSFOSC

µs

th(RSTL)in External reset pulse hold time

µs

RESET

VDD

WATCHDOG RESET

ST72XXX

LVD RESET

INTERNAL

RON

0.1

µF

VDD

0.1

µF

VDD

4.7k

Ω

EXTERNAL

RESET

CIRCUIT 8)

RESET CONTROL

USER

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