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ST72589BW bảng dữ liệu(PDF) 150 Page - STMicroelectronics |
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ST72589BW bảng dữ liệu(HTML) 150 Page - STMicroelectronics |
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150 / 158 page ![]() ST72589BW, ST72389BW 150/158 MEMORY AND PERIPHERAL CHARACTERISTICS - ADC WARNING ON ADC: The ST72E/T589BW5 EPROM devices have their ADC which differs from the ROM devices in term of accuracy (less precision), timing (slower stabilization and conver- sion time) and external components. Care must be taken at software and hardware application levels when transferring a code from the EPROM device to the ROM device. OE GE 1 LSB (ideal) 1LSB i deal V DDA V SSA – 256 ----------------------------------------- = Vin (LSBideal) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line TUE=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. OE=Offset Error: deviation between the first actual transition and the first ideal one. GE=Gain Error: deviation between the last ideal transition and the last actual one. DLE=Differential Linearity Error: maximum devia- tion between actual steps and the ideal one. ILE=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Digital Result ADCDR 255 254 253 5 4 3 2 1 0 7 6 123 456 7 253 254 255 256 (1) (2) TUE DLE ILE (3) VDDA VSSA ADC Analog to Digital Converter (8-bit) for ST72E/T589BW5 devices Symbol Parameter Conditions Min Typ Max Unit |TUE| Total unadjusted error* fADC=fCPU=4MHz VDD=VDDA=5V 2 LSB OE Offset error* -1 1 GE Gain Error* -2 2 |DLE| Differential linearity error* 1 |ILE| Integral linearity error* 2 VAIN Conversion range voltage VSSA VDDA V IADC A/D conversion supply current fADC=fCPU=4MHz VDD=VDDA=5V 1mA tSTAB Stabilization time after enable ADC 30 µs tLOAD Sample capacitor loading time 8 32 µs 1/fADC tCONV Hold conversion timeval 8 32 µs 1/fADC RAIN External input resistor 20 ΚΩ RADC Internal input resistor 18 ΚΩ CSAMPLE Sample capacitor 22 pF |
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