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ST72311R bảng dữ liệu(PDF) 103 Page - STMicroelectronics |
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ST72311R bảng dữ liệu(HTML) 103 Page - STMicroelectronics |
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103 / 164 page  ST72311R, ST72511R, ST72512R, ST72532R 103/164 SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres- caler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 54) is divided by the binary factor set in the ERPR register (in the range 1 to 255). The extended baud rate generator is not used af- ter a reset. EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (ETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate divi- sion factor for the transmit circuit. Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres- caler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 54) is divided by the binary factor set in the ETPR register (in the range 1 to 255). The extended baud rate generator is not used af- ter a reset. Table 22. SCI Register Map and Reset Values 70 ERPR 7 ERPR 6 ERPR 5 ERPR 4 ERPR 3 ERPR 2 ERPR 1 ERPR 0 70 ETPR 7 ETP R 6 ETPR 5 ETP R 4 ETPR 3 ETP R 2 ETPR 1 ETP R 0 Address (Hex.) Register Label 76543210 0050h SCISR Reset Value TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 00 0051h SCIDR Reset Value MSB x x x xx xx LSB x 0052h SCIBRR Reset Value SCP1 0 SCP0 0 SCT2 0 SCT1 0 SCT0 0 SCR2 0 SCR1 0 SCR0 0 0053h SCICR1 Reset Value R8 x T8 x0 M x WAKE x 000 0054h SCICR2 Reset Value TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 0055h SCIERPR Reset Value MSB 0 0 0 0000 LSB 0 0057h SCIETPR Reset Value MSB 0 0 0 0000 LSB 0 |
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