ST72260G datasheet(152/171 Pages) STMICROELECTRONICS

152 / 171 page

ST72260G, ST72262G, ST72264G

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13.12 10-BIT ADC CHARACTERISTICS

TA = -40°C to 85°C, unless otherwise specified

Figure 105. RAIN max. vs fADC with CAIN=0pF

Figure 106. Recommended CAIN/RAIN values

Figure 107. Analog Input equivalent circuit

Notes:

1. Data based on design simulation.

2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω). Data

based on characterization results, not tested in production.

3. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

4. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and

decreased to allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fADC

ADC clock frequency

0.41)

4MHz

VAIN

Conversion voltage range

VSS

VDD

CADC

Internal sample and hold capacitor

tCONV

Conversion time

fADC=4MHz

µs

112

1/fADC

RAIN

External input impedance

see

Figure

105 and

Figure

1062)3)4)

Ω

CAIN

External capacitor on analog input

fAIN

Variation frequency of analog input

signal

010

CPARASITIC (pF)

4 MHz

2 MHz

1 MHz

0.1

100

1000

0.01

0.1

fAIN(KHz)

Cain 10 nF

Cain 22 nF

Cain 47 nF

AINx

ST72XXX

VDD

±1

µA

0.6V

CADC

6pF

VAIN

RAIN

10-Bit A/D

Conversion

Ω(max)

CAIN

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