R5F5671CDDFB datasheet(134/179 Pages) RENESAS

134 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 134 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

2.4.7.11

SSIE

Figure 2.63

Clock Input Timing

Figure 2.64

SSIE Clock Input/Output Timing

Table 2.42

Expansion Serial Sound Interface Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

AUDIO_CLK

Cycle

tEXcyc

—

Figure 2.63

High/low level

tEXL/tEXH

0.4

0.6

tEXcyc

SSIBCK0

Cycle

Master

—

Figure 2.64

Slave

—

Output clock high level

Master

tHC

0.35

—

Output clock low level

tLC

0.35

—

Input clock high level

Slave

tHC

0.35

—

Input clock low level

tLC

0.35

—

Output clock rise time

Master

tRC

—0.15

Output clock fall time

tFC

—0.15

Input clock rise time

Slave

tRC

—0.15

Input clock fall time

tFC

—0.15

SSILRCK0,SSITXD0,

SSIRXD0

Input setup time

Master

tSR

—

Figure 2.65,

Figure 2.66

Slave

—

Input hold time

Master

tHR

8—

Slave

—

Output delay time

Master

tDTR

–10

Slave

Output delay time from when an

SSILRCK0 signal is changed

Slave

tDTRW

—

Figure 2.67

AUDIO_CLK

(input)

tEXH

tEXf

tEXL

1/2 VCC

tEXcyc

tEXr

SSIBCK0

tHC

tLC

tRC

tI, tO

tFC

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