R5F5651CDDFB datasheet(148/188 Pages) RENESAS

148 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 148 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.7.13

MMC

Note 1. tPBcyc: PCLKB cycle

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All MMC AC timings are measured in combination with the pins in the same group.

Figure 2.65

MMC Interface

Table 2.41

MMC Host Interface Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.*1

Max.

Unit

Test

Conditions*2

MMCIF MMC_CLK clock cycle

tMMCPP

2 × tPBcyc

—

Figure 2.65

MMC_CLK clock high level width

tMMCWH

6.5

—

MMC_CLK clock low level width

tMMCWL

6.5

—

MMC_CLK clock rising time

tMMCLH

—3

MMC_CLK clock falling time

tMMCHL

—3

MMC_CMD, MMC_D7 to MMC_D0 output data delay

(data transfer mode)

tMMCODLY

–6.6

6.6

MMC_CMD, MMC_D7 to MMC_D0 input data setup

tMMCISU

8—

MMC_CMD, MMC_D7 to MMC_D0 input data hold

tMMCIH

2.5

—

tMMCPP

tMMCWL

tMMCWH

tMMCHL

tMMCLH

tMMCISU

tMMCIH

tMMCODLY (max)

tMMCODLY (min)

MMC_CLK

MMC_CMD,

MMC_D7 to MMC_D0 input

MMC_CMD,

MMC_D7 to MMC_D0 output

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