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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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R5F5651CDDFB bảng dữ liệu(PDF) 133 Page - Renesas Technology Corp |
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R5F5651CDDFB bảng dữ liệu(HTML) 133 Page - Renesas Technology Corp |
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133 / 188 page  R01DS0276EJ0240 Rev.2.40 Page 133 of 188 Oct 31, 2023 RX65N Group, RX651 Group 2. Electrical Characteristics 2.4.7.9 SCI Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1 Table 2.35 SCIg, SCIh, and SCIi Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item Symbol Min. Max. Unit*1 Test Conditions SCIg, SCIh Input clock cycle Asynchronous tScyc 4 — tPBcyc Figure 2.46 Clock synchronous 6— Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous*2 tScyc 8— tPBcyc Clock synchronous 4— Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Clock synchronous tTXD — 28 ns Figure 2.47 Receive data setup time Clock synchronous tRXS 15 — ns Receive data hold time Clock synchronous tRXH 5— ns SCIi Input clock cycle Asynchronous tScyc 4— tPAcyc Figure 2.46 Clock synchronous 12 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous*2 tScyc 8— tPAcyc Clock synchronous 8— Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Master tTXD — 15 ns Figure 2.47 Slave — 28 Receive data setup time Clock synchronous tRXS 20 — ns Receive data hold time Clock synchronous tRXH 5— |
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