AS3715 datasheet(148/159 Pages) AMSOSRAM

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ams Datasheet

Page 147

[v1-03] 2015-Aug-10

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AS3715 − Application Information

PCB Routing Recommendations

Internal DCDC

Attention should be paid to the routing of the VSUP, LX and GND

traces of the DCDC converter.

• Keep the VSUP traces to the input capacitor as short as

possible. Do not use vias for this connection.

• Make a common ground area for the input cap, output cap

and PVSS terminal of the DCDC. Connect this ground area

with vias to the system ground plane.

• Use short wide traces for LX node. If you need to set vias,

use it on the LX trace and not on the capacitor

connections.

Power Stage Connections

To avoid cross talk to other lines a minimum spacing of

minimum 3W should be kept. For a proper DCDC operation it’s

recommended to avoid routing other clock traces being routed

in parallel (also on other layers) to the control lines.

Figure 185:

PCB Control Line Routing

PCB Control Line Routing: Shows an example PCB routing for the control lines of the multiphase controllers.

CTRL1&2, are not interfering with each other as they are

running at 180° phase shift. They can be routed with a minimum

spacing. The TEMP lines should be used as “guard traces” to

other control line pairs (e.g. CTRL3&4 or CTRL 5&6 or CTRL 7&8)

as well as to other sensitive or clock traces on the PCB. A

minimum spacing of >1.5W should be used as spacing between

TEMP and CTRL traces.

CTRL1

GND

εr

≥ 3W

> 1W

CTRL2

> 1.5W

TEMP1

> 1.5W

CTRL3

> 1W

CTRL4

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