DAC39RF10 datasheet(176/232 Pages) TI2

176 / 232 page

Table 8-73. NCO_SYNC Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1-0

NCO_SYNC_SRC

R/W

00b

If FR_EN=0:

This register determines how NCO synchronization events will

be triggered. This includes both accumulator resets specified by

NCO_AR and the application of changes to NCO_DITH_EN, FREQ,

and PHASE.

0: Setting SPI_SYNC will immediately perform specified events. (All

will occur in the same clock cycle.)

1: Setting SPI_SYNC will cause the specified events to occur on the

next SYSREF rising edge.

2: While SPI_SYNC is high, the specified events will occur on every

SYSREF rising edge.

3: While SPI_SYNC is high, the LSb of the “I” input to DUC0 will

cause the specified events. To trigger the event, the LSb must be low

for 4 or more consecutive samples and then high for 4 consecutive

samples. The sync will occur coincident with the 4th high sample

arriving at the DUC0 input.

If FR_EN=1:

This register determines how NCO synchronization events will

be triggered. This includes both accumulator resets specified by

FR_NCO_AR and the application of changes to FR_NCO_DITH_EN,

FR_FREQL, FR_FREQS, and FR_PHASE.

0: If FRS is set, the specified events is performed at the rising edge

of FRCS. (All will occur in the same clock cycle.)

1: Reserved

2: RESERVED

3: If FRS is set, the LSb of the “I” input to DUC0 will cause the

specified events following the rising edge of FRCS. To trigger the

event, the LSb must be low for 4 or more consecutive samples and

then high for 4 consecutive samples. The sync will occur coincident

with the 4th high sample arriving at the DUC0 input. While waiting

for the LSb trigger, zero will be used for the LSb data. The LSb will

immediately return to being used as data after the 4th consecutive

high sample.

Note: This register should only be changed when SPI_SYNC=0 and

the FR interface is idle (FRCS=1).

8.70 NCO_AR Register (Offset = 0303h) [reset = 0Fh]

NCO_AR is shown in Figure 8-72 and described in Table 8-74.

Return to the Register Summary Table.

NCO Accumulator Reset

Figure 8-72. NCO_AR Register

RESERVED

NCO_AR

R/W-0h

Table 8-74. NCO_AR Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

176

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