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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DAC39RF10 bảng dữ liệu(PDF) 161 Page - Texas Instruments |
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DAC39RF10 bảng dữ liệu(HTML) 161 Page - Texas Instruments |
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161 / 232 page  Table 8-43. LANE_EQS[15:0] Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 6 EQOVER[n] R EQOVER status for PHY lane n pre/post cursor analysis. See Pre/ Post Cursor Analysis Procedure. 5 EQUNDER[n] R EQUNDER status for PHY lane n pre/post cursor analysis. See Pre/ Post Cursor Analysis Procedure.. 4 EQLEVEL_S[n] R This field returns the equalizer level currently in effect for lane n. This is the count of the number of bits set in the thermometer encoded value from the stsrx EQLEVEL_S field for lane n. 8.41 ESRUN Register (Offset = 01F0h) [reset = 00h] ESRUN is shown in Figure 8-42 and described in Table 8-44. Return to the Register Summary Table. Eye-Scan Run Control Figure 8-42. ESRUN Register 7 6 5 4 3 2 1 0 RESERVED ESRUN R/W-00h R/W-0b Table 8-44. ESRUN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 ESRUN R/W 0b After setting up eye-scan, set ESRUN=1 to run the eye-scan test. See Eye Scan Procedure. 8.42 ES_CTRL Register (Offset = 01F1h) [reset = 00h] ES_CTRL is shown in Figure 8-43 and described in Table 8-45. Return to the Register Summary Table. Note: Only change this register while ESRUN=0. Eye-Scan Control Figure 8-43. ES_CTRL Register 7 6 5 4 3 2 1 0 RESERVED ESLEN ES R/W-00b R/W-00b R/W-0h Table 8-45. ES_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 ES_CTRL R/W 00b www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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