DAC39RF10 datasheet(152/232 Pages) TI2

152 / 232 page

Table 8-26. JTIMER Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2-0

JTT

R/W

JESD204C watchdog counter threshold. When the watchdog counter

reaches the threshold defined by JTT, the PHY layer is reset

(including the PHY PLL(s) if JTPLL=1) and the watchdog timer is

reset. Larger values of JTT cause the watchdog timer to take longer

to intervene.

JTT : Watchdog Counter Threshold : Counter Duration [assuming

FCLK = 10.24 GHz

0 : <Watchdog Timer Disabled> : <disabled>

1 : 217 : 102.4 μs

2 : 219 : 409.6 μs

3 : 232 : 1.63 ms

4 : 223 : 6.55 ms

5-7 : RESERVED : RESERVED

Note: The watchdog may not detect link up events shorter than 210

(1024) CLK cycles.

8.25 SYNC_EPW Register (Offset = 0127h) [reset = 00h]

SYNC_EPW is shown in Figure 8-26 and described in Table 8-27.

Return to the Register Summary Table.

JESD204C SYNC Error Report Pulse Width

Figure 8-26. SYNC_EPW Register

RESERVED

SYNC_EPW

R/W-00h

R/W-000b

Table 8-27. SYNC_EPW Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

RESERVED

R/W

00h

2-0

SYNC_EPW

R/W

000b

Specifies the pulse width of SYNC that is used for reporting errors

to the transmitter. When an error is detected that does not require

link resynchronization, SYNC is asserted for SYNC_EPW link clock

cycles (equal to 4*SYNC_EPW character durations). To disable

error reporting over SYNC, set SYNC_EPW=0. The legal range for

SYNC_EPW is 0 to 7.

Note: This register should only be changed when JESD_EN= 0.

8.26 CRC_TH Register (Offset = 0128h) [reset = 00h]

CRC_TH is shown in Figure 8-27 and described in Table 8-28.

Return to the Register Summary Table.

JESD204C CRC Error Thresholds

Figure 8-27. CRC_TH Register

RESERVED

CRC_ERR_REC

CFC_ERR_TH

R/W-0h

R/W-00b

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

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