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STM32MP151AAA3T bảng dữ liệu(PDF) 204 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Arm® Cortex®-A7 650 MHz Cortex®-M4 MPU, TFT, 35 comm. interfaces, 25 timers, adv. analog
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STM32MP151AAA3T bảng dữ liệu(HTML) 204 Page - STMicroelectronics

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Electrical characteristics
STM32MP151A
204/245
DS12500 Rev 1
6.3.30
Digital filter for sigma-delta modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 86 for DFSDM are derived from
tests performed under the ambient temperature, fpclkx frequency and VDD supply voltage
summarized in Table 13: General operating conditions, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5×VDD
Refer to Section 0.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for
DFSDMx).
Table 86. DFSDM measured timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDFSDMCLK
DFSDM clock
1.71 V < VDD < 3.6 V
-
-
fSYSCLK
MHz
fCKIN
(1/TCKIN)
Input clock
frequency
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.71 V < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]
≠0),
1.71 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]
≠0),
2.7 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
fCKOUT
Output clock
frequency
1.71 < VDD < 3.6 V
-
-
20
DuCyCKOUT
Output clock
frequency duty
cycle
1.71 < VDD < 3.6 V
45
50
55
%



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