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STM32F429NET7 bảng dữ liệu(PDF) 181 Page - STMicroelectronics

tên linh kiện STM32F429NET7
Giải thích chi tiết về linh kiện  ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT
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STM32F429NET7 bảng dữ liệu(HTML) 181 Page - STMicroelectronics

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STM32F427xx STM32F429xx
Electrical characteristics
192
NAND controller waveforms and timings
Figure 69 through Figure 72 represent synchronous waveforms, and Table 100 and
Table 101 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
•
COM.FMC_SetupTime = 0x01;
•
COM.FMC_WaitSetupTime = 0x03;
•
COM.FMC_HoldSetupTime = 0x02;
•
COM.FMC_HiZSetupTime = 0x01;
•
ATT.FMC_SetupTime = 0x01;
•
ATT.FMC_WaitSetupTime = 0x03;
•
ATT.FMC_HoldSetupTime = 0x02;
•
ATT.FMC_HiZSetupTime = 0x01;
•
Bank = FMC_Bank_NAND;
•
MemoryDataWidth = FMC_MemoryDataWidth_16b;
•
ECC = FMC_ECC_Enable;
•
ECCPageSize = FMC_ECCPageSize_512Bytes;
•
TCLRSetupTime = 0;
•
TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
Table 99. Switching characteristics for PC Card/CF read and write cycles
in I/O space(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NIOWR)
FMC_NIOWR low width
8THCLK − 0.5
-
ns
tv(NIOWR-D)
FMC_NIOWR low to FMC_D[15:0] valid
-
0
ns
th(NIOWR-D)
FMC_NIOWR high to FMC_D[15:0] invalid
9THCLK − 2-
ns
td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid
-
5THCLK
ns
th(NCEx-NIOWR)
FMC_NCEx high to FMC_NIOWR invalid
5THCLK
-ns
td(NIORD-NCEx)
FMC_NCEx low to FMC_NIORD valid
-
5THCLK
ns
th(NCEx-NIORD)
FMC_NCEx high to FMC_NIORD) valid
6THCLK+2
-
ns
tw(NIORD)
FMC_NIORD low width
8THCLK − 0.5
8THCLK+0.5
ns
tsu(D-NIORD)
FMC_D[15:0] valid before FMC_NIORD high
THCLK
-ns
td(NIORD-D)
FMC_D[15:0] valid after FMC_NIORD high
0
-
ns
1. CL = 30 pF.
2. Guaranteed by characterization results.



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