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230 / 231 page  Revision history STM32F427xx STM32F429xx 230/231 DocID024030 Rev 6 17-Sep-2015 6 Updated notes related to the minimum and maximum values guaranteed by design, characterization or test in production. Updated IDD_STOP_UDM in Table 27: Typical and maximum current consumptions in Stop mode. Removed note related to tests in production in Table 24: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM and Table 26: Typical and maximum current consumption in Sleep mode. Updated Table 41: HSI oscillator characteristics. Figure 31 renamed HSI deviation vs. temperature and updated. Updated Figure 38: SPI timing diagram - slave mode and CPHA = 0. Updated Section : Ethernet characteristics. Updated Table 43: Main PLL characteristics, Table 44: PLLI2S (audio PLL) characteristics and Table 45: PLLISAI (audio and LCD-TFT PLL) characteristics. Removed note 1 in Table 75: ADC static accuracy at fADC = 18 MHz, Table 76: ADC static accuracy at fADC = 30 MHz and Table 77: ADC static accuracy at fADC = 36 MHz. Updated td(SDCLKL _Data) and th(SDCLKL _Data) in Table 104: SDRAM write timings. Added Figure 96: UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint and Table 117: UFBGA169 recommended PCB design rules (0.5 mm pitch BGA). Added Figure 99: UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint and Table 119: UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA). Table 124. Document revision history Date Revision Changes |
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