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STM32F427AI bảng dữ liệu(PDF) 141 Page - STMicroelectronics

tên linh kiện STM32F427AI
Giải thích chi tiết về linh kiện  ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32F427AI bảng dữ liệu(HTML) 141 Page - STMicroelectronics

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STM32F427xx STM32F429xx
Electrical characteristics
192
Figure 38. SPI timing diagram - slave mode and CPHA = 0
tv(SO)
th(SO)
Data output valid/hold
time
Slave mode (after enable edge),
SPI1/4/5/6 and 2.7V ≤ VDD ≤ 3.6V
-11
13
ns
Slave mode (after enable edge),
SPI2/3, 2.7 V≤VDD≤3.6 V
-14
15
Slave mode (after enable edge),
SPI1/4/5/6, 1.7 V≤VDD≤3.6 V
-15.5
19
Slave mode (after enable edge),
SPI2/3, 1.7 V≤VDD≤3.6 V
-
15.5
17.5
tv(MO)
Data output valid time
Master mode (after enable edge),
SPI1/4/5/6, 2.7 V≤VDD≤3.6 V
--
2.5
Master mode (after enable edge),
SPI1/2/3/4/5/6, 1.7 V≤VDD≤3.6 V
--
4.5
th(MO)
Data output hold time
Master mode (after enable edge)
0
-
-
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Table 62. SPI dynamic characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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