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STM32F412RGH7TR bảng dữ liệu(PDF) 164 Page - STMicroelectronics

tên linh kiện STM32F412RGH7TR
Giải thích chi tiết về linh kiện  Arm®-Cortex®-M4 32b MCUFPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces
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STM32F412RGH7TR bảng dữ liệu(HTML) 164 Page - STMicroelectronics

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Electrical characteristics
STM32F412xE/G
164/201
DocID028087 Rev 7
6.3.26
SD/SDIO MMC/eMMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 96 for the SDIO are derived from
tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage
conditions summarized in Table 16, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Table 95. Synchronous non-multiplexed PSRAM write timings(1)(2)
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
2THCLK – 0.5
-
ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)
-
1
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2)
THCLK + 0.5
-
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
-
1
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
0
-
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
-
2
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
THCLK
-
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
-
1.5
td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high
THCLK + 0.5
-
td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low
-
4
td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low
-
3
td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high
THCLK
-
tsu(NWAIT-
CLKH)
FSMC_NWAIT valid before FSMC_CLK high
2
-
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
2
-



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