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STM32F412RGH6PTR bảng dữ liệu(PDF) 114 Page - STMicroelectronics

tên linh kiện STM32F412RGH6PTR
Giải thích chi tiết về linh kiện  Arm®-Cortex®-M4 32b MCUFPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces
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STM32F412RGH6PTR bảng dữ liệu(HTML) 114 Page - STMicroelectronics

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Electrical characteristics
STM32F412xE/G
114/201
DocID028087 Rev 7
Table 46. PLLI2S (audio PLL) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLI2S_IN
PLLI2S input clock(1)
-0.95(2)
12.10
MHz
fPLLI2S_OUT
PLLI2S multiplier output clock
-
-
-
216
fVCO_OUT
PLLI2S VCO output
-
100
-
432
tLOCK
PLLI2S lock time
VCO freq = 100 MHz
75
-
200
µs
VCO freq = 432 MHz
100
-
300
Jitter(3)
Master I2S clock jitter
Cycle to cycle at
12.288 MHz on
48 kHz period,
N=432, R=5
RMS
-
90
-
peak
to
peak
-
±280
-
ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90
-
WS I2S clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-
400
-
IDD(PLLI2S)(4)
PLLI2S power consumption on
VDD
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
IDDA(PLLI2S)(4)
PLLI2S power consumption on
VDDA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Guaranteed by characterization, not tested in production.



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