LAN9252VSLASHML datasheet(219/329 Pages) MICROCHIP

tên linh kiện	LAN9252V/ML

Giải thích chi tiết về linh kiện	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

Scroll/Zoom	100%

nhà sản xuất	MICROCHIP [Microchip Technology]

Trang chủ	http://www.microchip.com

Logo

219 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 219

LAN9252

12.13.5

ETHERCAT PROCESS RAM READ ADDRESS AND LENGTH REGISTER

(ECAT_PRAM_RD_ADDR_LEN)

This read/write register is used in conjunction with the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_-

DATA) and the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) to perform read operations

from the EtherCAT Core Process RAM.

Offset:

308h

Size:

32 bits

Note:

The starting byte address and length must be programmed with valid values such that all transfers are

within the bounds of the Process RAM address range of 1000h to 1FFFh.

Bits

Description

Type

Default

31:16

PRAM Read Length (PRAM_READ_LEN)

This field indicates the number of bytes to be read from the EtherCAT Core

Process RAM. It is decremented as data is read from the EtherCAT Core and

placed into the FIFO.

The host should not modify this field unless the PRAM Read Busy

(PRAM_READ_BUSY) bit is a low.

R/W

0000h

15:0

PRAM Read Address (PRAM_READ_ADDR)

This field indicates the EtherCAT Core byte address to be read. It is incre-

mented as data is read from the EtherCAT Core and placed into the FIFO.

Note:

The Process RAM starts at address 1000h.

The host should not modify this field unless the PRAM Read Busy

(PRAM_READ_BUSY) bit is a 0.

R/W

0000h

LAN9252V/ML bảng dữ liệu(PDF) 219 Page - Microchip Technology