LAN9252VSLASHML datasheet(206/329 Pages) MICROCHIP

tên linh kiện	LAN9252V/ML

Giải thích chi tiết về linh kiện	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

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nhà sản xuất	MICROCHIP [Microchip Technology]

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LAN9252

DS00001909A-page 206

 2015 Microchip Technology Inc.

12.9.7

EXTERNAL PHY TIMING

Since the EtherCAT Core does not use the PHY transmit clock, proper timing must be ensured based on the common

25 MHz reference clock (which is output to the external PHY via the MII_CLK25 pin). To aid in this, the EtherCAT Core

has the TX shift feature enabled. This feature can delay the generation of the transmit signals from the EtherCAT Core

by 0ns, 10ns, 20ns or 30ns. This value is manually set using tx_shift_strap[1:0].

12.9.7.1

MII Connection Timing

The MII interface TX and RX timing is as follows:

Note 1:

Timing is designed for a system load between 10 pF and 25 pF.

Note 2:

Assumes TX shift value of 2, add 10 ns for each increment of TX shift (shift values of 3, 0, and 1 in order).

FIGURE 12-7:

MII TX TIMING

TABLE 12-4:

MII TX TIMING VALUES

Symbol

Description

Min

Max

Units

Notes

tclkp

MII_CLK25 period

tclkh

MII_CLK25 high time

tclkp * 0.45 tclkp * 0.55

tclkl

MII_CLK25 low time

tclkp * 0.45 tclkp * 0.55

tval

MII_TXD[3:0], MII_TXEN output valid from rising edge

of MII_CLK25 Note 2

10.0

Note 1

thold

MII_TXD[3:0], MII_TXEN output hold from rising edge

of MII_CLK25 Note 2

Note 1

MII_CLK25

MII_TXD[3:0]

MII_TXEN

tclkh

tclkl

tclkp

tval

thold

(output)

tval

thold

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