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ST10F271Z1T3 bảng dữ liệu(PDF) 165 Page - STMicroelectronics

tên linh kiện ST10F271Z1T3
Giải thích chi tiết về linh kiện  16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
PDF  173 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST10F271Z1T3 bảng dữ liệu(HTML) 165 Page - STMicroelectronics

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ST10F271
Electrical characteristics
165/173
1.
Partially tested, guaranteed by design characterization.
Figure 59.
External bus arbitration (releasing the bus)
1.
The ST10F271 will complete the currently running bus cycle before granting bus access.
2.
This is the first possibility for BREQ to become active.
3.
The CS outputs will be resistive high (pull-up) after t64.
Table 80.
External bus arbitration timings
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64MHz
min.
max.
min.
max.
t61
SR
HOLD input setup time
to CLKOUT
18.5–18.5–
ns
t62
CC
CLKOUT to HLDA high
or BREQ low delay
–
12.5
–
12.5
ns
t63
CC
CLKOUT to HLDA low
or BREQ high delay
–
12.5
–
12.5
ns
t64
CC
CSx release 1)
–20
–
20
ns
t65
CC
CSx drive
– 415– 415
ns
t66
CC
Other signals release 1)
–20
–
20
ns
t67
CC
Other signals drive
– 4
15
– 4
15
ns
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)



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