STM32H563IIK6 datasheet(208/270 Pages) STMICROELECTRONICS

208 / 270 page

Electrical characteristics

STM32H562xx and STM32H563xx

208/270

DS14258 Rev 5

Note:

ADC accuracy vs. negative injection current: injecting a negative current on any analog

input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to

ground) to analog pins, which may potentially inject negative currents.

Figure 56. ADC accuracy characteristics

1. Example of an actual transfer curve.

2. Ideal transfer curve.

3. End point correlation line.

4. ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

5. EO = Offset error: deviation between the first actual transition and the first ideal one.

6. EG = Gain error: deviation between the last ideal transition and the last actual one.

7. ED = Differential linearity error: maximum deviation between actual steps and the ideal one.

8. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation

line.

Figure 57. Typical connection diagram when using the ADC with FT/TT pins

featuring analog switch function

1. Refer to Table 95 for the values of RAIN, and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

MSv19880V6

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End-point correlation line

n = ADC resolution

ET = total unadjusted error: maximum deviation

between the actual and ideal transfer curves

EO = offset error: maximum deviation between the first

actual transition and the first ideal one

EG = gain error: deviation between the last ideal

transition and the last actual one

ED = differential linearity error: maximum deviation

between actual steps and the ideal one

EL = integral linearity error: maximum deviation between

any actual transition and the end point correlation line

n-1

Output code

VSSA

n-2

n-3

VREF+ (VDDA)

1 LSB ideal

(1)

(2)

(3)

(or

)]

[1LSB =

VDDA

VREF+

MSv67871V3

Sample-and-hold ADC converter

Converter

Cparasitic

(2)

Ilkg

(3)

CADC

VDDA

(4)

RAIN

(1)

VAIN

RADC

VREF+

(4)

VSSA

I/O

analog

switch

Sampling

switch with

multiplexing

VSS

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