PC312XDP512F0CFVR datasheet(948/1350 Pages) FREESCALE

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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

948

Freescale Semiconductor

23.0.5.47 Port H Input Register (PTIH)

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can also be used to detect

overload or short circuit conditions on output pins.

23.0.5.48 Port H Data Direction Register (DDRH)

Read: Anytime.

Write: Anytime.

This register configures each port H pin as either input or output.

If the associated routed SPI module is enabled this register has no effect on the pins.

The SCI forces the I/O state to be an output for each port line associated with an enabled output ( TXD4).

It also forces the I/O state to be an input for each port line associated with an enabled input ( RXD4). In

those cases the data direction bits will not change.

If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.

The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral modules are

disabled.

76543210

PTIH7

PTIH6

PTIH5

PTIH4

PTIH3

PTIH2

PTIH1

PTIH0

Reset1

1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the

associated pin values.

————————

= Unimplemented or Reserved

Figure 23-49. Port H Input Register (PTIH)

76543210

DDRH7

DDRH6

DDRH5

DDRH4

DDRH3

DDRH2

DDRH1

DDRH0

Reset

00000000

Figure 23-50. Port H Data Direction Register (DDRH)

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