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ST10F273 bảng dữ liệu(PDF) 170 Page - STMicroelectronics

tên linh kiện ST10F273
Giải thích chi tiết về linh kiện  16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
PDF  179 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST10F273 bảng dữ liệu(HTML) 170 Page - STMicroelectronics

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Electrical characteristics
ST10F273
170/179
24.8.19
External bus arbitration
VDD = 5V
± 10%, V
SS = 0V, TA = -40°C to +125°C, CL = 50pF
Figure 57.
External bus arbitration (releasing the bus)
1.
The ST10F273 will complete the currently running bus cycle before granting bus access.
2.
This is the first possibility for BREQ to become active.
3.
The CS outputs will be resistive high (pull-up) after t64.
Table 80.
External bus arbitration timings
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64 MHz
Min.
Max.
Min.
Max.
t61
SR
HOLD input setup time
to CLKOUT
18.5–18.5–
ns
t62
CC
CLKOUT to HLDA high
or BREQ low delay
–
12.5
–
12.5
t63
CC
CLKOUT to HLDA low
or BREQ high delay
–
12.5
–
12.5
t64
CC
CSx release(1)
1.
Partially tested, guaranteed by design characterization
–20
–
20
t65
CC
CSx drive
– 415– 415
t66
CC
Other signals release(1)
–20
–
20
t67
CC
Other signals drive
– 4
15
– 4
15
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)



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