ST10F273 datasheet(145/179 Pages) STMICROELECTRONICS

tên linh kiện	ST10F273

Giải thích chi tiết về linh kiện	16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

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ST10F273

Electrical characteristics

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24.8.2

Definition of internal timing

The internal operation of the ST10F273 is controlled by the internal CPU clock fCPU. Both

edges of the CPU clock can trigger internal (for example pipeline) or external (for example

bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time

between two consecutive edges of the CPU clock, called “TCL”.

The CPU clock signal can be generated by different mechanisms. The duration of TCL and

its variation (and also the derived external timing) depends on the mechanism used to

generate fCPU.

This influence must be regarded when calculating the timings for the ST10F273.

The example for PLL operation shown in Figure 43 refers to a PLL factor of 4.

The mechanism used to generate the CPU clock is selected during reset by the logic levels

on pins P0.15-13 (P0H.7-5).

Figure 43.

Generation mechanisms for the CPU clock

TCLTCL

fCPU

fXTAL

fCPU

fXTAL

Phase locked loop operation

Direct clock drive

TCL

fCPU

fXTAL

Prescaler operation

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