RELEASED

PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

viii

FIG. 23 ANY-PHY INTERFACE, OUTPUT BUS SLAVE TRANSFER TIMING 208

FIG. 24 CLOCKED SERIAL DATA TRANSMIT INTERFACE .......................... 208

FIG. 25 CLOCKED SERIAL DATA TRANSMIT INTERFACE, 1 BIT GAP ...... 209

FIG. 26 CLOCKED SERIAL DATA TRANSMIT INTERFACE, 8 BIT GAP ....... 209

FIG. 27 CLOCKED SERIAL DATA RECEIVE INTERFACE............................. 209

FIG. 28: MICROPROCESSOR INTERFACE READ TIMING.......................... 216

FIG. 29: MICROPROCESSOR INTERFACE WRITE TIMING ........................ 218

FIG. 30: RSTB TIMING ................................................................................... 219

FIG. 31: INGRESS SCI-PHY/ANY-PHY INTERFACE TIMING........................ 220

FIG. 32: EGRESS SCI-PHY/ANY-PHY INTERFACE TIMING......................... 221

FIG. 33: CLOCKED SERIAL DATA INTERFACE ............................................ 222

FIG. 34: JTAG PORT INTERFACE TIMING.................................................... 224