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ICS1893CF bảng dữ liệu(PDF) 109 Page - Integrated Circuit Systems

tên linh kiện ICS1893CF
Giải thích chi tiết về linh kiện  3.3-V 10Base-T/100Base-TX Integrated PHYceive
PDF  126 Pages
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nhà sản xuất  ICST [Integrated Circuit Systems]
Trang chủ  http://www.icst.com
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ICS1893CF bảng dữ liệu(HTML) 109 Page - Integrated Circuit Systems

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Chapter 9 DC and AC Operating Conditions
ICS1893CF, Rev. F, 03/01/07
Mar. 2007
109
ICS1893CF Data Sheet Rev. F - Release
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
9.5.7 MII Management Interface Timing
Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of
timings of signals on the MDC and MDIO pins). Figure 9-8 shows the timing diagram for the time periods.
† The ICS1893CF is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading
of MDC.
Figure 9-8. MII Management Interface Timing Diagram
Table 9-14. MII Management Interface Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
MDC Minimum High Time
160
ns
t2
MDC Minimum Low Time
160
ns
t3
MDC Period
400†
ns
t4
MDC Rise Time to MDIO Valid
0
300
ns
t5
MDIO Setup Time to MDC
10
ns
t6
MDIO Hold Time after MDC
10
ns
MDC
MDIO
(Output)
MDC
MDIO
(Input)
t1
t2
t3
t4
t5
t6



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