H838024 datasheet(135/697 Pages) RENESAS

tên linh kiện	H838024

Giải thích chi tiết về linh kiện	Renesas 8-Bit Single-Chip Microcomputer Super Low Power Series

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Section 3 Exception Handling

Rev. 7.00 Mar 10, 2005 page 93 of 652

REJ09B0042-0700

• If the interrupt request is accepted, after processing of the current instruction is completed,

both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in

figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be

executed upon return from interrupt handling.

• The I bit of CCR is set to 1, masking further interrupts.

• The vector address corresponding to the accepted interrupt is generated, and the interrupt

handling routine located at the address indicated by the contents of the vector address is

executed.

Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when

clearing bits in an interrupt request register, always do so while interrupts are masked

(I = 1).

2. If the above clear operations are performed while I = 0, and as a result a conflict arises

between the clear instruction and an interrupt request, exception processing for the

interrupt will be executed after the clear instruction has been executed.

H838024 bảng dữ liệu(PDF) 135 Page - Renesas Technology Corp