PIC18F258-ESLASHLSQTP datasheet(128/402 Pages) MICROCHIP

128 / 402 page

PIC18FXX8

DS41159E-page 126

15.3

Compare Mode

In Compare mode, the 16-bit CCPR1 and ECCPR1

TMR1 register pair value or the TMR3 register pair

value. When a match occurs, the CCP1 pin can have

one of the following actions:

• Driven high

•Driven low

• Toggle output (high-to-low or low-to-high)

• Remains unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0. At the same time, interrupt flag

bit CCP1IF is set.

15.3.1

CCP1 PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the appropriate TRISC bit.

15.3.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

15.3.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen, the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

15.3.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets either

the TMR1 or TMR3 register pair. Additionally, the

ECCP1 special event trigger will start an A/D

conversion if the A/D module is enabled.

FIGURE 15-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default low level. This is not the data latch.

Note:

The special event trigger from the ECCP1

module will not set the Timer1 or Timer3

interrupt flag bits.

Special Event Trigger will:

Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)

Set bit GO/DONE which starts an A/D conversion (ECCP1 only)

Note

I/O pins have diode protection to VDD and VSS.

TMR1H

TMR1L

TMR3H

TMR3L

CCPR1H

CCPR1L

Comparator

T3ECCP1

T3CCP1

Output

Logic

Special Event Trigger

Match

CCP1

CCP1CON<3:0>

Mode Select

Output Enable

Set Flag bit CCP1IF

(PIR1<2>)

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