PIC18F258-ESLASHLSQTP datasheet(254/402 Pages) MICROCHIP

254 / 402 page

PIC18FXX8

DS41159E-page 252

FIGURE 21-3:

COMPARATOR OUTPUT BLOCK DIAGRAM

21.6

Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that occurred. The CMIF

bit (PIR2 register) is the Comparator Interrupt Flag. The

CMIF bit must be reset by clearing ‘0’. Since it is also

possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

The CMIE bit (PIE2 register) and the PEIE bit (INTCON

the GIE bit must also be set. If any of these bits are

clear, the interrupt is not enabled, though the CMIF bit

will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of CMCON will end the

mismatch condition.

Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

To RE1 or

RE2 pin

Bus

Data

Read CMCON

Set

MULTIPLEX

CMIF

bit

Port Pins

Read CMCON

Reset

From

Other

Comparator

CxINV

Note:

If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR2

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