PCF5083HSLASH5V2SLASHF3 datasheet(105/136 Pages) PHILIPS

105 / 136 page

1996 Oct 29

105

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

Table 84 Combined Interrupt Register

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

Table 85 High Priority Interrupt Register

Notes

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

2. To clear these interrupt flags, the corresponding location has to be written with a logic 1.

BIT

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

HWCTRL_INT

HWCTRL_INT interrupt was activated.

−−

IOM_INT

IOM_INT interrupt was activated.

−−

SI_INT

SI_INT interrupt was activated.

−−

R/W

HWCTRL_MASK

Enable the HWCTRL_INT interrupt to assert the

COMB_INT interrupt line.

−

R/W

IOM_MASK

Enable the IOM_INT interrupt to assert the COMB_INT

interrupt line.

−

R/W

SI_MASK

Enable the SI_INT interrupt to assert the COMB_INT

interrupt line.

−

BIT

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

R/W

RX_INT(2)

Assert the HIPR_INT interrupt line when the RX_REG

is sent via the RF Bus.

−

R/W

RXTX_INT(2)

Assert the HIPR_INT interrupt line when the TX_REG

is sent via the RF Bus prior to a MON burst in the TX

timeslot.

−

R/W

TX_INT(2)

Assert the HIPR_INT interrupt line when the TX_REG

is sent via the RF Bus prior to a TX burst.

−

R/W

MON_INT(2)

Assert the HIPR_INT interrupt line when the

MON_REG is sent via the RF Bus.

−

R/W

AS_INT1(2)

Assert the HIPR_INT interrupt line when the

DACOFF_REG is sent via the RF Bus.

−

R/W

FRAME_INT(2)

Assert the HIPR_INT interrupt line at the beginning of

every TDMA frame.

−

PIRQN_INT

Assert the HIPR_INT interrupt line if the DSP core host

port input request is active.

−

PORQN_INT

Assert the HIPR_INT interrupt line if the DSP core host

port output request is active.

−

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