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M700000002 bảng dữ liệu(PDF) 121 Page - SPANSION

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Giải thích chi tiết về linh kiện  2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
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November 25, 2003
Am70PDL127BDH/Am70PDL129BDH
119
AD VAN C E
INFORM ATION
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
6. AC Specifications listed are tested with V
IO = VCC. Contact AMD for information on AC operation with VIO
≠ V
CC.
Parameter
Speed Options
JEDEC
Std.
Description
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
110
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
45
ns
t
DVEH
t
DS
Data Setup Time
Min
45
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
45
ns
t
EHEL
t
CPH
CE# Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2, 3)
Typ
352
µs
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Typ
22
µs
µs
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
17.6
µs
µs
Single Word/Byte Program
Operation (Note 2, 5)
Word
Typ
100
µs
Single Word/Byte Accelerated
Programming Operation (Note 2,
5)
Word
Typ
90
µs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
t
RH
RESET# High Time Before Write
Min
50
ns



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