AT89C5131A-RDTIL datasheet(174/185 Pages) ATMEL

174 / 185 page

174

AT89C5131A-L

4338E–USB–06/06

Timings

Test conditions: capacitive load on all pins= 50 pF.

Table 128. SPI Interface Master AC Timing

VDD = 2.7 to 5.5 V, TA = -40 to +85°C

Note:

PER is XTAL period when SPI interface operates in X2 mode or twice XTAL period when SPI inter-

face operates in X1 mode.

Symbol

Parameter

Min

Max

Unit

Slave Mode

TCHCH

Clock Period

TPER

TCHCX

Clock High Time

0.8

TPER

TCLCX

Clock Low Time

0.8

TPER

TSLCH, TSLCL

SS Low to Clock edge

100

TIVCL, TIVCH

Input Data Valid to Clock Edge

TCLIX, TCHIX

Input Data Hold after Clock Edge

TCLOV, TCHOV

Output Data Valid after Clock Edge

TCLOX, TCHOX

Output Data Hold Time after Clock Edge

TCLSH, TCHSH

SS High after Clock Edge

TSLOV

SS Low to Output Data Valid

4TPER+20

TSHOX

Output Data Hold after SS High

2TPER+100

TSHSL

SS High to SS Low

2TPER+120

TILIH

Input Rise Time

μs

TIHIL

Input Fall Time

μs

TOLOH

Output Rise time

100

TOHOL

Output Fall Time

100

Master Mode

TCHCH

Clock Period

TPER

TCHCX

Clock High Time

2TPER-20

TCLCX

Clock Low Time

2TPER-20

TIVCL, TIVCH

Input Data Valid to Clock Edge

TCLIX, TCHIX

Input Data Hold after Clock Edge

TCLOV, TCHOV

Output Data Valid after Clock Edge

TCLOX, TCHOX

Output Data Hold Time after Clock Edge

AT89C5131A-RDTIL bảng dữ liệu(PDF) 174 Page - ATMEL Corporation

AT89C5131A-RDTIL bảng dữ liệu(HTML) 174 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL