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ST72F262G2B6 bảng dữ liệu(PDF) 157 Page - STMicroelectronics |
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ST72F262G2B6 bảng dữ liệu(HTML) 157 Page - STMicroelectronics |
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157 / 172 page ![]() ST72260Gx, ST72262Gx, ST72264Gx 157/172 13.12 10-BIT ADC CHARACTERISTICS VDD= 2.7 to 5.5V, TA = -40°C to 85°C, unless otherwise specified Figure 97. RAIN max. vs fADC with CAIN=0pF 2) Figure 98. Recommended CAIN/RAIN values 3) Figure 99. Analog Input equivalent circuit Notes: 1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k Ω). Data based on characterization results, not tested in production. 2. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca- pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 3. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and decreased to allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz. Symbol Parameter Conditions Min Typ Max Unit fADC ADC clock frequency 0.5 4MHz VAIN Conversion voltage range VSS VDD V CADC Internal sample and hold capacitor 6 pF tCONV Conversion time FLASH, fADC=4MHz 28 µs 112 1/fADC ROM, fADC=4MHz 3.5 µs 14 1/fADC RAIN External input impedance see Figure 97 and Figure 981)2)3) k Ω CAIN External capacitor on analog input pF fAIN Variation frequency of analog input signal Hz 0 5 10 15 20 25 30 35 40 45 010 30 70 CPARASITIC (pF) 4 MHz 2 MHz 1 MHz 0.1 1 10 100 1000 0.01 0.1 1 10 fAIN(KHz) Cain 10 nF Cain 22 nF Cain 47 nF AINx ST72XXX VDD IL ±1 µA VT 0.6V VT 0.6V CADC 6pF VAIN RAIN 10-Bit A/D Conversion 2k Ω(max) CAIN |
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