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ST72F262G2B6 bảng dữ liệu(HTML) 143 Page - STMicroelectronics |
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143 / 172 page  ST72260Gx, ST72262Gx, ST72264Gx 143/172 EMC CHARACTERISTICS (Cont’d) 13.7.3.2 Static and Dynamic Latch-Up ■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. ■ DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical Sensitivities Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). Symbol Parameter Conditions Class 1) LU Static latch-up class TA=+25°C TA=+85°C A A DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A |
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