ST72340 datasheet(154/191 Pages) STMICROELECTRONICS

154 / 191 page

ST72340, ST72344, ST72345

154/191

13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions

TA = -40 to +85°C unless otherwise specified.

Note:

When the power supply is between 2.7 and 2.95V (VIT+(LVD) max), the device is either in the guaranteed

functional area or in reset state, thus allowing deterministic application behaviour. However the LVD may

generate a reset below 2.95V and the user should therefore not use the device below this level when the

LVD is enabled.

Figure 84. fCPU Maximum Operating Frequency Versus VDD Supply Voltage

13.3.2 Low Voltage Detector (LVD) Thresholds

TA = -40 to +85°C unless otherwise specified

Note:

1. Not tested in production, guaranteed by design

Symbol

Parameter

Conditions

Min

Max

Unit

VDD

Supply voltage

fCPU = 8 MHz. max.

3.3

5.5

fCPU = 4 MHz. max.

2.7

5.5

fOSC

External clock frequency

3.3V

≤ V

DD≤5.5V

Up to 16

MHz

2.7V

≤V

DD<3.3V

Up to 8

fCPU [MHz]

SUPPLY VOLTAGE [V]

4.0

4.5

5.0

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

5.5

3.6

FUNCTIONALITY

GUARANTEED

IN THIS AREA

3.3

2.7

CAUTION: RESET MAY

BE ACTIVATED BY LVD

IN THIS AREA

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

High Threshold

Med. Threshold

Low Threshold

3.85

3.24

2.60

4.20

3.56

2.88

4.61

3.90

3.14

VIT-(LVD)

Reset generation threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

3.66

3.04

2.45

3.98

3.36

2.71

4.36

3.66

2.95

Vhys(LVD)

LVD voltage threshold hysteresis

VIT+(LVD)-VIT-(LVD)

200

VtPOR

VDD rise time rate

20 1)

100 1)

ms/V

tg(VDD)

VDD glitches filtered by LVD

150

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