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CS5535 bảng dữ liệu(PDF) 392 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện CS5535
Giải thích chi tiết về linh kiện  Geode??CS5535 I/O Companion Multi-Function South Bridge
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CS5535 bảng dữ liệu(HTML) 392 Page - National Semiconductor (TI)

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Revision 0.8
UART/IR Controller Register Descriptions (Continued)
5.12.9.2
SIR Pulse Width Register (SIR_PW)
SIR_PW sets the pulse width for transmitted pulses in SIR operation mode. These settings do not affect the receiver. Upon
reset, the content of this register is 00h, which defaults to a pulse width of 3/16 of the baud rate.
5.12.9.3
Bank Select Register (BSR)
BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 5.12.3.4 "Link Control/Bank Select Regis-
ters" on page 373 for bit descriptions.
I/O Offset
02h
Type
R/W
Reset Value
00h
SIR_PW Register Map
76
54
32
10
RSVD
SPW[3:0]
SIR_PW Bit Descriptions
Bit
Name
Description
7:4
RSVD
Reserved. Write to 0.
3:0
SPW[3:0]
SIR Pulse Width. Two codes for setting the pulse width are available. All other values for
this field are reserved.
0000: Pulse width = 3/16 of bit period (Default).
1101: Pulse width = 1.6 µs.
I/O Offset
03h
Type
R/W
Reset Value
00h



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