CS5535 datasheet(314/555 Pages) NSC

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314

Revision 0.8

DIVIL Register Descriptions (Continued)

DIVIL_LBAR_FLSH[x] Bit Descriptions

Bit

Name

Description

If bit 34 = 0; I/O Mapped

63:49

RSVD

Reserved. Reads return value written. Defaults to 0

RSVD

Reserved. Always write 0.

47:36

IO_MASK

I/O Address Mask Value. For standard NAND Flash, bits [48:36] should be set to all

1s. Add 0s from the LSBs as needed for OEM specific devices that take more than 16

bytes.See discussion in Section 4.6.1 "LBARs and Comparators" on page 97

RSVD

Reserved. Reads return value written. Defaults to 0.

MEM_IO

Memory or I/O Mapped.

0: LBAR is I/O mapped).

1: LBAR is memory mapped.

NOR_NAND

NOR or NAND.

0: Use NOR chip select (FLASH_CS[x]#).

1: Use NAND chip select (FLASH_CE[x]#).

LBAR_EN

LBAR Enable.

0: Disable LBAR.

1: Enable LBAR.

31:17

RSVD

Reserved. Reads return value written. Defaults to 0.

RSVD

Reserved. Always write 0.

15:4

BASE_ADDR

Base Address in I/O Space. See discussion in Section 4.6.1 "LBARs and Compara-

tors" on page 97

3:0

RSVD

Reserved. Reads return value written. Defaults to 0.

If bit 34 = 1; Memory Mapped

63:44

MEM_MASK

Memory Address Mask Value. See discussion in Section 4.6.1 "LBARs and Compar-

ators" on page 97

43:35

RSVD

Reserved. Reads return value written. Defaults to 0.

MEM_IO

Memory or I/O Mapped.

0: LBAR is I/O mapped.

1: LBAR is memory mapped.

NOR_NAND

NOR or NAND.

0: Use NOR chip select (FLASH_CS[x]#).

1: Use NAND chip select (FLASH_CE[x]#).

LBAR_EN

LBAR Enable.

0: Disable LBAR.

1: Enable LBAR.

31:12

BASE_ADDR

Base Address in Memory Space. See discussion in Section 4.6.1 "LBARs and Com-

parators" on page 97

11:0

RSVD

Reserved. Reads return value written. Defaults to 0.

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