DSPIC30F datasheet(132/220 Pages) MICROCHIP

132 / 220 page

dsPIC30F5011/5013

DS70116C-page 130

Preliminary

 2004 Microchip Technology Inc.

19.7

A/D Acquisition Requirements

The analog input model of the 12-bit A/D converter is

shown in Figure 18-11. The total sampling time for the

A/D is a function of the internal amplifier settling time

and the holding capacitor charge time.

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the voltage level on the analog input

pin. The source impedance (RS), the interconnect

impedance (RIC), and the internal sampling switch

(RSS) impedance combine to directly affect the time

required to charge the capacitor CHOLD. The combined

impedance of the analog sources must therefore be

small enough to fully charge the holding capacitor

within the chosen sample time. To minimize the effects

of pin leakage currents on the accuracy of the A/D con-

verter, the maximum recommended source imped-

ance, RS, is 2.5 k

Ω. After the analog input channel is

selected (changed), this sampling function must be

completed prior to starting the conversion. The internal

holding capacitor will be in a discharged state prior to

each sample operation.

FIGURE 19-2:

12-BIT A/D CONVERTER ANALOG INPUT MODEL

CPIN

ANx

VT = 0.6V

I leakage

RIC

≤ 250Ω

Sampling

Switch

RSS

CHOLD

= DAC capacitance

VSS

VDD

= 18 pF

± 500 nA

Legend: CPIN

I leakage

RIC

RSS

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch resistance

= sample/hold capacitance (from DAC)

various junctions

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs

≤ 2.5 kΩ.

RSS

≤ 3 kΩ

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