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S71GS256 bảng dữ liệu(PDF) 123 Page - SPANSION

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October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
123
Ad vance
Info rmat i o n
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part
of the memory array required by the host system. The refresh options are full ar-
ray, one-half array, one-quarter array, three-quarters array, or none of the array.
The mapping of these partitions can start at either the beginning or the end of
the address map (see Table 23 through Table 25).
Table 22. Refresh Configuration Register Mapping
Table 23. 128Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
ADDRESS SPACE
SIZE
DENSITY
0
0
0
Full die
000000h–7FFFFFh
8 Meg x 16
128Mb
0
0
1
One-half of die
000000h–3FFFFFh
4 Meg x 16
64Mb
0
1
0
One-quarter of die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
1
1
One-eighth of die
000000h–0FFFFFh
1 Meg x 16
16Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
400000h–7FFFFFh
4 Meg x 16
64Mb
1
1
0
One-quarter of die
600000h–7FFFFFh
2 Meg x 16
32Mb
1
1
1
One-eighth of die
700000h–7FFFFFh
1 Meg x 16
16Mb
PAR
A4
A3
A2
A1
A0
Read Configuration
Register
Address Bus
A5
A6
All must be set to "0"
0
1
Deep Power-Down
DPD Enable
DPD Disable (default)
RCR[4]
A[18:8]
Register
Select
Reserved
Reserved
Reserved
TCR
A[22:20]
A19
0
1
Register Select
Select RCR
Select BCR
RCR[19]
All must be set to "0"
RCR[1] RCR[0]
Refresh Coverage
RCR[2]
0
0
Full array (default)
0
0
1
Bottom 1/2 array
0
1
0
Bottom 1/4 array
0
1
1
Bottom 1/8 array
0
01
1
Top 1/2 array
10
1
Top 1/4 array
DPD
Must be set to "0"
A7
Page
0
1
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enable
RCR[7]
4
51
2
30
6
18–8
19
22–20
7
1
None of array
00
1
Top 3/4 array
11
RCR[6]
RCR[5]
Maximum Case Temp
+85ºC (default)
11
00
01
10
+70ºC
+45ºC
+15ºC



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