ICS1893CFILF datasheet(109/127 Pages) RENESAS

tên linh kiện	ICS1893CFILF

Giải thích chi tiết về linh kiện	3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

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Chapter 9 DC and AC Operating Conditions

ICS1893CF, Rev. K, 05/13/10

May, 2010

109

ICS1893CF Data Sheet Rev. J - Release

9.5.7 MII Management Interface Timing

Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of

timings of signals on the MDC and MDIO pins). Figure 9-8 shows the timing diagram for the time periods.

† The ICS1893CF is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading

of MDC.

Figure 9-8. MII Management Interface Timing Diagram

Table 9-14. MII Management Interface Timing

Time

Period

Parameter

Conditions

Min.

Typ.

Max.

Units

MDC Minimum High Time

–

160

–

MDC Minimum Low Time

–

160

–

MDC Period

–

400†

†

–

MDC Rise Time to MDIO Valid

–

300

MDIO Setup Time to MDC

–

MDIO Hold Time after MDC

–

MDC

MDIO

(Output)

MDC

MDIO

(Input)

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