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ST72325 bảng dữ liệu(PDF) 153 Page - STMicroelectronics

tên linh kiện ST72325
Giải thích chi tiết về linh kiện  8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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CLOCK CHARACTERISTICS (Cont’d)
12.5.5 Clock Security System (CSS)
Note:
1. Data based on characterization results.
12.5.6 PLL Characteristics
Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 78 shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-
cies of less than 125KHz, the jitter is negligible.
Figure 78. Integrated PLL Jitter vs signal frequency1
Note 1: Measurement conditions: fCPU = 8MHz.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSFOSC
Safe Oscillator Frequency 1)
3MHz
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fOSC
PLL input frequency range
2
4
MHz
∆ fCPU/ fCPU Instantaneous PLL jitter 1)
fOSC = 4 MHz.
0.7
2
%
0
0.2
0.4
0.6
0.8
1
1.2
4 MHz
2 MHz
1 MHz 500 kHz 250 kHz 125 kHz
Application Frequency
+/-Jitter (%)
Max
Typ



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