HC705CT4GRSSLASHD datasheet(102/152 Pages) NXP

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Comparators

General Release Specification

MC68HC705CT4 — Rev. 2.0

102

Comparators

MOTOROLA

CM3IE — Comparator 3 Interrupt Enable

This control bit, when set, allows CMP3 to generate an interrupt when

it goes high.

CEN3 — Comparator 3 Enable

This control bit, when set, powers up the voltage comparator 3 on

PD0. The user must set this bit to allow any functionality of the

comparator. After enabling the comparator, the user should delay for

tCEN before reading the state of the output or enabling the interrupt.

Reset clears this bit.

PD0 remains under control of its DDR bit to enable the user to drive

CMP3+ to a desired level. When CEN3 is cleared, the comparator is

disabled and consumes negligible power.

CEN2 — Comparator 2 Enable

This control bit, when set, powers up the voltage comparator 2 on

PD2 and PD3. The user must set this bit to allow any functionality of

the comparator. After enabling the comparator, the user should delay

for tCEN before reading the state of the output. Reset clears this bit.

PD2 and PD3 remain under control of their DDR bits to enable the

user to drive CMP2– and CMP12+ to desired levels. When CEN2 is

cleared, the comparator is disabled and consumes negligible power.

CEN1 — Comparator 1 Enable

This control bit, when set, powers up voltage comparator 1 on PD1

and PD2. The user must set this bit to allow any functionality of the

comparator. After enabling the comparator, the user should delay for

tCEN before reading the state of the output. Reset clears this bit.

PD1 and PD2 remain under control of their DDR bits to enable the

user to drive CMP1– and CMP12+ to desired levels. When CEN1 is

cleared, the comparator is disabled and consumes negligible power.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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