HC705C9AGRSSLASHD datasheet(139/157 Pages) NXP

tên linh kiện	HC705C9AGRS/D

Giải thích chi tiết về linh kiện	General Release Specification

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General Release Specification

Control Timing

MC68HC705C9A — Rev. 2.0

Electrical Specifications

Figure 12-5. External Interrupt Timing

Figure 12-6. STOP Recovery Timing Diagram

IRQ

tILIH

tILIL

tILIH

IRQ PIN

IRQ1

IRQN

a. Edge-Sensitive Trigger Condition. The minimum pulse width (t

ILIH) is either 125 ns (fOP = 2.1 MHz)

or 250 ns (f

OP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to

execute the interrupt service routine plus 19 t

CYC cycles.

b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low,

(INTERNAL)

NORMALLY

USED WITH

WIRED-OR

CONNECTION

the next interrupt is recognized

ILIH

4064 t

CYC

OSC1

RESET

IRQ2

IRQ3

INTERNAL

CLOCK

NOTES:

1. Represents the internal clocking of the OSC1 pin

2. IRQ pin edge-sensitive mask option

3. IRQ pin level- and edge-sensitive mask option

4. RESET vector address shown for timing example

RESET OR INTERRUPT

VECTOR FETCH

3FFE

3FFF4

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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