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STM32U545NET6QTR bảng dữ liệu(PDF) 247 Page - STMicroelectronics

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STM32U545NET6QTR bảng dữ liệu(HTML) 247 Page - STMicroelectronics

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DS14216 Rev 1
247/283
STM32U545xx
Electrical characteristics
258
Figure 50. PSSI receive timing diagram
5.3.31
Timer characteristics
The parameters given in the following tables are specified by design, not tested in
production.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
MSv63436V1
ts(DATA)
CKPOL=0
CKPOL=1
PSSI D[15:0]
(input)
th(DATA)
tw(PDCKL)
tw(PDCKH)
tc(PDCK)
tf(PDCK)
Invalid data IN
Valid data IN
DEPOL=0
DEPOL=1
RDYPOL=0
RDYPOL=1
Invalid data IN
tr(PDCK)
ts(DE)
th(DE)
tv(RDY)
tho(RDY)
Table 123. TIMx(1) characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tres(TIM)
Timer resolution time
-1
-
tTIMxCLK
fTIMxCLK = 160 MHz
6.25
-
ns
fEXT
Timer external clock frequency on
CH1 to CH4
-0
fTIMxCLK/2
MHz
fTIMxCLK = 160 MHz
0
80
ResTIM
Timer resolution
TIMx (except TIM2/3/4/5)
-
16
bit
TIM2/3/4/5
-
32
tCOUNTER 16-bit counter clock period
-
1
65536
tTIMxCLK
fTIMxCLK = 160 MHz
0.007
409.6
µs
tMAX_COUNT
Maximum possible count with
32-bit counter
-
-
65536 × 65536 tTIMxCLK
fTIMxCLK = 160 MHz
-
26.843
s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.



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