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UPSD325X bảng dữ liệu(PDF) 141 Page - STMicroelectronics

tên linh kiện UPSD325X
Giải thích chi tiết về linh kiện  Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
PDF  176 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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UPSD325X bảng dữ liệu(HTML) 141 Page - STMicroelectronics

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µPSD325X DEVICES
Table 105. Status During Power-on RESET, Warm RESET and Power-down Mode
Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to ’0’ on Power-on RESET or Warm RESET.
Port Configuration
Power-On RESET
Warm RESET
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD Mode)
Address Out
Tri-stated
Tri-stated
Not defined
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-On RESET
Warm RESET
Power-down Mode
PMMR0 and PMMR2
Cleared to ’0’
Unchanged
Unchanged
Macrocells flip-flop status
Cleared to ’0’ by internal
Power-on RESET
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register1
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to ’0’
Cleared to ’0’
Unchanged



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