UPSD325X datasheet(117/176 Pages) STMICROELECTRONICS

117 / 176 page

117/176

µPSD325X DEVICES

Example. FS0 is valid when the address is in the

range of 8000h to BFFFh, CSBOOT0 is valid from

8000h to 9FFFh, and RS0 is valid from 8000h to

87FFh. Any address in the range of RS0 always

accesses the SRAM. Any address in the range of

CSBOOT0 greater than 87FFh (and less than

9FFFh) automatically addresses secondary Flash

memory segment 0. Any address greater than

9FFFh accesses the primary Flash memory seg-

ment 0. You can see that half of the primary Flash

memory segment 0 and one-fourth of secondary

Flash memory segment 0 cannot be accessed in

this example.

Note: An equation that defined FS1 to anywhere

in the range of 8000h to BFFFh would

not be valid.

Figure 54 shows the priority levels for all memory

components. Any component on a higher level can

overlap and has priority over any component on a

lower level. Components on the same level must

not overlap. Level one has the highest priority and

level 3 has the lowest.

Memory Select Configuration in Program and

Data Spaces. The MCU Core has separate ad-

dress spaces for Program memory and Data

memory. Any of the memories within the PSD

MODULE can reside in either space or both spac-

es. This is controlled through manipulation of the

VM Register that resides in the CSIOP space.

The VM Register is set using PSDsoft Express to

have an initial value. It can subsequently be

changed by the MCU so that memory mapping

can be changed on-the-fly.

For example, you may wish to have SRAM and pri-

mary Flash memory in the Data space at Boot-up,

and secondary Flash memory in the Program

space at Boot-up, and later swap the primary and

secondary Flash memories. This is easily done

with the VM Register by using PSDsoft Express

Configuration to configure it for Boot-up and hav-

ing the MCU change it when desired. Table 89 de-

scribes the VM Register.

Figure 54. Priority Level of Memory and I/O

Components in the PSD MODULE

Table 89. VM Register

Level 1

SRAM, I /O, or

Peripheral I /O

Level 2

Secondary

Non-Volatile Memory

Highest Priority

Lowest Priority

Level 3

Primary Flash Memory

AI02867D

Bit 7

PIO_EN

Bit 6

Bit 5

Bit 4

Primary

FL_Data

Bit 3

Secondary Data

Bit 2

Primary

FL_Code

Bit 1

Secondary Code

Bit 0

SRAM_Code

0 = disable

PIO Mode

not used

0 = RD

can’t

access

Flash

memory

0 = RD can’t

access Secondary

Flash memory

0 = PSEN

can’t

access

Flash

memory

0 = PSEN can’t

access Secondary

Flash memory

0 = PSEN

can’t

access

SRAM

1= enable

PIO Mode

not used

1 = RD

access

Flash

memory

1 = RD access

Secondary Flash

memory

1 = PSEN

access

Flash

memory

1 = PSEN access

Secondary Flash

memory

1 = PSEN

access

SRAM

UPSD325X bảng dữ liệu(PDF) 117 Page - STMicroelectronics

UPSD325X bảng dữ liệu(HTML) 117 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL