AM6412...ALV datasheet(178/244 Pages) TI

178 / 244 page

Table 7-76. MMC1 DLL Delay Mapping for all Timing Modes (continued)

MMCSD1_SS_PHY_CTRL_4_REG

MMCSD1_SS_PHY_CTRL_5_REG

BIT FIELD

[20]

[15:12]

[8]

[4:0]

[2:0]

BIT FIELD NAME

OTAPDLYENA OTAPDLYSEL ITAPDLYENA

ITAPDLYSEL

CLKBUFSEL

MODE

DESCRIPTION

DELAY

ENABLE

DELAY

VALUE

INPUT

DELAY

ENABLE

INPUT

DELAY

VALUE

DELAY

BUFFER

DURATION

UHS-I

DR50

4-bit PHY operating

1.8 V, 50 MHz

0x1

0x9

0x1

Tuning(1)

0x7

UHS-I

SDR104

4-bit PHY operating

1.8, V 200 MHz

0x1

0x6

0x1

Tuning(1)

0x7

(1)

Tuning means this mode requires a tuning algorithm to be used for optimal input timing

Table 7-77 presents timing conditions for MMC1.

Table 7-77. MMC1 Timing Conditions

PARAMETER

MIN

MAX UNIT

Input Conditions

SRI

Input slew rate

Default Speed, High Speed

0.69

2.06

V/ns

UHS–I SDR12, UHS–I SDR25

0.34

1.34

V/ns

UHS–I DDR50

V/ns

Output Conditions

Output load capacitance

UHS–I DDR50

All other modes

PCB Connectivity Requirements

td(Trace Delay)

Propagation delay of each trace

UHS–I DDR50

240

1134

All other modes

126

1386

td(Trace Mismatch

Delay)

Propagation delay mismatch across all

traces

UHS–I DDR50, UHS–I SDR104

All other modes

100

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

178

Submit Document Feedback

Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411

AM6412...ALV bảng dữ liệu(PDF) 178 Page - Texas Instruments

AM6412...ALV bảng dữ liệu(HTML) 178 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL